PE43503MLI-Z【PDF 6/11 页】IC RF DSA 5BIT 50 OHM 24QFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录56

2页 3页 4页 5页 [6页]7页 8页 9页 10页

Product Specification

PE43503

Page 6 of 11

Document No. 70-0252-05 UltraCMOS" RFIC Solutions

Programming Options

Parallel/Serial Selection

Either a parallel or serial interface can be used to

control the PE43503. The P/S bit provides this

selection, with P/S=LOW selecting the parallel

interface and P/S=HIGH selecting the serial

interface.

Parallel Mode Interface

The parallel interface consists of five CMOS-

compatible control lines that select the desired

attenuation state, as shown in Table 7.

The parallel interface timing requirements are

defined by Fig. 16 (Parallel Interface Timing

Diagram), Table 11 (Parallel Interface AC

Characteristics), and switching speed (Table 1).

For latched-parallel programming the Latch Enable

(LE) should be held LOW while changing attenuation

state control values, then pulse LE HIGH to LOW

(per Fig. 16) to latch new attenuation state into

device.

For direct parallel programming, the Latch Enable

(LE) line should be pulled HIGH. Changing

attenuation state control values will change device

state to new attenuation. Direct Mode is ideal for

manual control of the device (using hardwire,

switches, or jumpers).

Serial Interface

The serial interface is a 8-bit serial-in, parallel-out

shift register buffered by a transparent latch. The 8-

bits make up the Attenuation Word that controls the

DSA. Fig. 15 illustrates a example timing diagram for

programming a state. When the DSA is used in

serial mode, ground all parallel control pins (pins 19-

23).

The serial-interface is controlled using three CMOS-

compatible signals: Serial-In (SI), Clock (CLK), and

Latch Enable (LE). The SI and CLK inputs allow

data to be serially entered into the shift register.

Serial data is clocked in LSB first.

The shift register must be loaded while LE is held

LOW to prevent the attenuator value from changing

as data is entered. The LE input should then be

toggled HIGH and brought LOW again, latching the

new data into the DSA. Attenuation Word truth table

is listed in Table 8. A programming example of the

serial register is illustrated in Table 9. The serial

timing diagram is illustrated in Fig. 15. It is required

that all parallel pins be grounded when the DSA is

used in serial mode.

Power-up Control Settings

The PE43503 will always initialize to the maximum

attenuation setting (31 dB) on power-up for both the

serial and latched-parallel modes of operation and

will remain in this setting until the user latches in the

next programming word. In direct-parallel mode, the

DSA can be preset to any state within the 31 dB

range by pre-setting the parallel control pins prior to

power-up. In this mode, there is a 400-祍 delay

between the time the DSA is powered-up to the time

the desired state is set. During this power-up delay,

the device attenuates to the maximum attenuation

setting (31 dB) before defaulting to the user defined

state. If the control pins are left floating in this mode

during power-up, the device will default to the

minimum attenuation setting (insertion loss state).

Dynamic operation between serial and parallel

programming modes is possible.

If the DSA powers up in serial mode (P/S = HIGH),

all the parallel control inputs DI[6:2] must be set to

logic low. Prior to toggling to parallel mode, the DSA

must be programmed serially to ensure D[7] is set to

logic low.

If the DSA powers up in either latched or direct-

parallel mode, all parallel pins DI[6:2] must be set to

logic low prior to toggling to serial mode (P

= HIGH), and held low until the DSA has been

programmed serially to ensure bit D[7] is set to logic

low.

The sequencing is only required once on power-

up. Once completed, the DSA may be toggled

between serial and parallel programming modes at

will.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式